The present invention relates to a process for etching dielectric layers on a substrate.
Dielectric material, such as silicon dioxide, silicon nitride, or TEOS deposited glass, is used in integrated circuits to electrically isolate active devices or features formed on a semiconductor substrate. For example, a layer of dielectric material can be used to electrically isolate electrically conductive interconnect lines that electrically connect active devices on the substrate. It is often necessary to etch through these dielectric layers to form holes or xe2x80x9cviasxe2x80x9d into which conducting material is deposited to make vertical interconnection or xe2x80x9ccontact plugs.xe2x80x9d To etch the dielectric layer, a mask layer of an etch-resistant material is deposited on the dielectric layer and patterned using conventional photolithographic methods to conform to a desired pattern of holes. In conventional etching processes, the dielectric layer is typically etched in a process chamber using a plasma of etchant gases. For example, a silicon dioxide layer is etched by a plasma of fluorine-containing gas that reacts with silicon in the dielectric layer to form volatile SiFx species. Suitable fluorine-containing gases include, for example, CHF3, CH3F, CF4, and CH2F2. In addition, the etchant gas contains passivating gases that combine with other vaporized gaseous species to form passivating deposits on the freshly etched features to provide anisotropic etching of the features.
The demand for faster integrated circuits in recent years has produced higher circuit densities and operating frequencies or clock speeds, resulting in the need for dielectric materials having a low dielectric constant (low K); i.e., in current semiconductor fabrication terminology, a low K material is a material that has a dielectric constant of less than about 3.2 which is the dielectric constant of silicon oxide, and more preferably from about 2.5 to 3.2. In high density integrated circuits, the metal interconnect lines are positioned closer together and carry voltages at higher frequencies. The relatively high dielectric constants of conventional dielectric materials allow polarization of the dielectric layer and crosstalk between the interconnect lines. Thus materials having low K are necessary to reduce capacitive coupling between interconnect lines in order to use the highest possible operating frequencies. New low K dielectric materials typically comprise organic polymers such as benzocyclobutene, parylene, polytetrafluoroethylene, polyether, or polyimide. In addition, low K dielectric materials often include small amounts of other materials, such as elemental silicon or silicon-containing compounds, for example Si, SiO2, or Si3N4 to provide increased thermal stability and adhesion to a variety of metals and oxides.
As with the silicon oxide materials, the low K dielectric materials are also etched using a plasma of a fluorine-containing gas, especially low K dielectric materials which contain silicon, such as benzocyclobutene, because the fluorine plasma readily reacts with the silicon-containing dielectric. However, it is difficult for the fluorine-containing gas compositions to provide both a high etch rate and a high etching selectivity ratio. By etching selectivity ratio it is meant the ratio of the rate of etching of the low K dielectric layer to the rate of etching of the overlying mask layer (which is typically silicon dioxide), or an underlying silicon-containing layer, such as silicon, polysilicon layer, or titanium silicide. Tailoring the gas composition to provide a high etch-rate often results in a low etching selectivity ratio, and vice versa. Modern integrated circuits typically require etching selectivity ratios of greater than 5:1 with respect to the mask layer, and 15:1 or greater with respect to adjacent and underlying silicon-containing layers such as polysilicon, WSix, and TiSix. The low selectivity ratio of conventional etching techniques, using fluorine-containing gases, make it especially difficult to anisotropically etch features having high aspect ratios, such as vias, in low K dielectric layers. Furthermore, fluorine-containing gases erode the process chamber, for example, highly reactive atomic fluorine species react with aluminum in process chambers to form volatile aluminum fluoride species, such as AIFx. Thus it is desirable to have an etching process for etching low dielectric materials that is absent fluorine and that provides high etch rates and a high etching selectivity ratio.
Another problem with conventional processes for etching low K dielectric material is that the etching processes fail to maintain the critical dimensions of etched features, which are the predefined dimensions of the etched features used to determine their electrical properties in the design of integrated circuits. In modern integrated circuits, the line widths of interconnect lines and diameters of contact plugs are becoming increasingly smaller to levels below 0.25 microns, to accommodate higher circuit densities. Because the electrical resistance of these features is proportional to the cross-sectional area of the etched features, it is important to maintain consistent and uniform dimensions without variations across an etched feature or between different etched features. Tapering cross-sectional profiles, that vary as a function of the spacing between the features or other variations in the profile of the features, are not acceptable. The critical dimensions are typically measured as a ratio or difference between the width Wr of the mask or resist features and the width We of the resultant etched features. The closer the two widths, the more predictable and reliable are the electrical properties of the etched features.
Another problem with conventional etching processes arises from excessive deposition of the passivating or other etchant deposits on the etched features or holes in the dielectric layer. These passivating deposits must be removed prior to filling the etched holes with electrically conductive material. While the precise composition of the passivating deposits depends upon the vaporized species in the process gas, the material being etched, and the mask or resist layer applied on the substrate, the passivating deposits typically consist of polymeric material. Because of their chemical composition, the passivating deposits are often difficult to remove without further etching or damaging the low K dielectric material. Thus it is desirable to have an etching process for etching a low K dielectric material that removes the passivating deposits while etching the substrate.
Yet another problem arises because it is difficult to form interconnect lines and vias in a low K dielectric layer by conventional processes, such as for example, a dual damascene method. A dual damascene process is a multilevel interconnect fabrication process in which a dielectric layer is etched to form first voids for fabricating vias that connect different levels of interconnecting lines, and second voids to fabricate interconnect lines. After the first voids are etched, the voids are filled with a sacrificial material, such as a photoresist comprising an organic polymer, which is resistant to the etchant gas. Then, the dielectric layer is etched a second time to form second voids for the interconnect lines which overlie the first voids. Thereafter, the sacrificial material is removed from the first voids, by dipping the substrate in an etchant solution. The first and second voids for the vias and lines are filled with metal in a single metallization step. However, when a low K dielectric material is used for the dielectric layer, it is difficult to use conventional dual damascene techniques because the same etchant solution that removes the sacrificial material will also often remove the low K dielectric material because both materials are organic polymers.
Accordingly, there is a need for an etching process for anisotropically etching low K dielectric material that provides a high etching rate and etching selectivity ratio relative to the overlying mask layer or underlying silicon-containing layer. It is desirable for the etching process to leave little or no passivating deposits on the substrate after etching is completed. It is also desirable that the etching plasma be absent fluorine-containing gas which erodes the process chamber. There is a further need for a process for forming low K dielectrics layers by a conventional dual damascene process.
This invention provides a method for etching a dielectric layer on a substrate, such as a silicon-containing organic dielectric layer, to provide a high etching selectivity to an overlying mask. The method comprises the steps of (i) placing a substrate having a dielectric layer covered by a mask of silicon oxide or silicon nitride into a process zone, (ii) providing in the process zone, an energized process gas comprising oxygen to etch the dielectric layer on the substrate substantially without etching the patterned mask layer of silicon oxide or silicon nitride. Preferably, the process gas introduced into the process zone is substantially absent a fluorine-containing gas. More preferably, the process gas further comprises a non-reactive gas, such as nitrogen, argon, xenon, neon, krypton, or helium, in a volumetric flow ratio of oxygen to non-reactive gas sufficiently high to etch the dielectric layer at an etch rate at least about 500 nm/minute and an etching selectivity of the dielectric layer to the mask of at least about 15:1. Most preferably, the is directed to etching a silicon-containing organic dielectric layer having a dielectric constant of less than about 3.0. Suitable organic dielectric layers are composed of a polymer comprising one or more of benzocyclobutene, parylene, polytetrafluoroethylene, polyether, or polyimide.
In another aspect, the present invention is directed to a method suitable for forming interconnect plugs in a dielectric layer on a substrate. In this method, a substrate having a dielectric layer and an overlying first mask is placed in a process zone. Using the etching process of the present invention, first voids are formed in the dielectric layer. The first voids are then filled with a sacrificial material that is etched at the same or lower rate than the material of the dielectric layer. The dielectric layer is etched a second time to form second voids for the interconnect lines, which overlie the first voids formed for the vias. Thereafter, the sacrificial material is removed from the first voids by dipping the substrate in a stripper solution. Then the first and second voids are filled with metal in a single metallization step to form interconnect plugs and interconnecting lines.